Module selection for pipelined synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Sehwa: a program for synthesis of pipelines
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
System synthesis using behavioural descriptions
EURO-DAC '90 Proceedings of the conference on European design automation
CASCH: a scheduling algorithm for "high level"-synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Debugging of behavioral VHDL specifications by source level emulation
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Execution interval analysis under resource constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Co-emulation and debugging of HW/SW-systems
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Resource sharing in hierarchical synthesis
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Breakpoints and breakpoint detection in source-level emulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Target architecture oriented high-level synthesis for multi-FPGA based emulation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Hardware resource allocation for hardware/software partitioning in the LYCOS system
Proceedings of the conference on Design, automation and test in Europe
Cross-level hierarchical high-level synthesis
Proceedings of the conference on Design, automation and test in Europe
Breakpoints and Breakpoint Detection in Source Level Emulation
ISSS '96 Proceedings of the 9th international symposium on System synthesis
A unified approach for scheduling and allocation
Integration, the VLSI Journal
Automated generation of custom processor core from C code
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
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