The ADAM advanced design automation system: overview, planner and natural language interface
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Improving the throughput of a pipeline by insertion of delays
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Predicting area-time tradeoffs for pipelined design
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Integrated scheduling and binding: a synthesis approach for design space exploration
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Move frame scheduling and mixed scheduling-allocation for the automated synthesis of digital systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Fast and near optimal scheduling in automatic data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Automatic module allocation in high level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Generating pipelined datapaths using reduction techniques to shorten critical paths
EURO-DAC '92 Proceedings of the conference on European design automation
Design of Testable Multipliers for Fixed-Width Data Paths
IEEE Transactions on Computers
DSS: A Distributed High-Level Synthesis System
IEEE Design & Test
Synthesis of Testable Pipelined Datapaths Using Genetic Search
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A design representation for high level synthesis
EURO-DAC '90 Proceedings of the conference on European design automation
CASCH: a scheduling algorithm for "high level"-synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Area-efficient arithmetic expression evaluation using deeply pipelined floating-point cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A heuristic scheduler for port-constrained floating-point pipelines
International Journal of Reconfigurable Computing
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This paper describes a set of techniques for the synthesis of pipelined data paths, and presents Sehwa, a program which performs such synthesis. The task includes the generation of data paths from a data flow graph along with a clocking scheme which overlaps execution of multiple tasks. Some examples which Sehwa has designed are given. Sehwa can find the minimum cost design, the highest performance design, and other designs between these two in the design space. We believe Sehwa to be the first pipelined synthesis program published in the open literature. Sehwa is written in Franz LISP, and executes within minutes for problems of practical size on a VAX 11/750.