A knowledge based system for selecting a test methodology for a PLA
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
The construction of minimal area power and ground nets for VLSI circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Talking to UNIX in English: an overview of UC
Communications of the ACM
A general methodology for synthesis and verification of register-transfer designs
DAC '84 Proceedings of the 21st Design Automation Conference
Predicting area-time tradeoffs for pipelined design
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
PHRAN-SPAN: a natural language interface for system specifications
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Sehwa: A program for synthesis of pipelines
25 years of DAC Papers on Twenty-five years of electronic design automation
An object oriented approach to CAD tool control within a design framework
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
FACE core environment: the model and its application in CAE/CAD tool development
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Representing conditional branches for high-level synthesis applications
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Design version management in the GARDEN framework
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A design utility manager: the ADAM planning engine
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Synthesis of VLSI systems with the CAMAD design aid
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Sehwa: a program for synthesis of pipelines
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Knowledge-Based System for Selecting Test Methodologies
IEEE Design & Test
Guest Editor's Introduction: Putting Synthesis to Work
IEEE Design & Test
A Synthesis Environment for Designing DSP Systems
IEEE Design & Test
A Model-Based Expert System for Digital System Design
IEEE Design & Test
DSS: A Distributed High-Level Synthesis System
IEEE Design & Test
Hierarchical Modeling of the VLSI Design Process
IEEE Expert: Intelligent Systems and Their Applications
Generic design flows for project management in a framework environment
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A Hierarchical Register Optimization Algorithm for Behavioral Synthesis
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Automatic knowledge acquisition in a digital circuit design system
EURO-DAC '90 Proceedings of the conference on European design automation
A design representation for high level synthesis
EURO-DAC '90 Proceedings of the conference on European design automation
Phrasal analysis of long noun sequences
ACL '87 Proceedings of the 25th annual meeting on Association for Computational Linguistics
Understanding system specifications written in natural language
IJCAI'87 Proceedings of the 10th international joint conference on Artificial intelligence - Volume 2
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This paper describes ADAM, an integrated Advanced Design AutoMation system, with focus on the knowledge-based synthesis subsystem. Working parts of this subsystem include a number of design activities and utilities, and a unified, multidimensional, hierarchical design representation. Two aspects of the synthesis subsystem are described in detail: the design planner and the natural language interface. The planner builds a plan for synthesis and analysis activities, drawing inferences from a knowledge base represented by a semantic net. The natural language interface accepts system-level behavioral specifications. Both of these packages are currently being implemented.