Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
The combination of scheduling, allocation, and mapping in a single algorithm
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Distributed design-space exploration for high-level synthesis systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The system architect's workbench
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The ADAM advanced design automation system: overview, planner and natural language interface
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Sehwa: a program for synthesis of pipelines
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A Synthesis Environment for Designing DSP Systems
IEEE Design & Test
Distributed design-space exploration for high-level synthesis systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Experiences in functional validation of a high level synthesis system
DAC '93 Proceedings of the 30th international Design Automation Conference
Synthesis of VHDL concurrent processes
EURO-DAC '94 Proceedings of the conference on European design automation
Hierarchical behavioral partitioning for multicomponent synthesis
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Accounting for various register allocation schemes during post-synthesis verification of RTL designs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs
IEEE Transactions on Computers
On the verification of synthesized designs using automatically generated transformational witnesses
Proceedings of the conference on Design, automation and test in Europe
Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs
Formal Methods in System Design - Special issue on formal methods for computer-added design
Formal Methods in System Design
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Verification of Basic Block Schedules Using RTL Transformations
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Transformations for functional verification of synthesized designs
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Clock-Skew Constrained Cell Placement
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Synchronous Controller Models for Synthesis from Communicating VHDL Processes
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Net Clustering Based Macrocell Placement
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
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DSS, a large-scale ongoing exercise in developing parallel algorithms for high-level synthesis and implementing them in an integrated distributed system to evaluate their individual and collective effectiveness, is discussed. Embedded in a very-high-speed integrated circuit hardware description language (VHDL) centered design environment, DSS consists of a collection of parallel algorithms executing on a multiple input, multiple data (MIMD) multiprocessor machine. The system uses coarse-grained parallelism to explore and evaluate many alternative VLSI designs efficiently. DSSs internal organization and its scheduling, register optimization, interconnection formation, and controller generation techniques are described. Results illustrating DSS performance with respect to design quality, and the efficiency of the DSS algorithms in a multiprocessor environment are presented.