An efficient method of partitioning circuits for multiple-FPGA implementation.
DAC '93 Proceedings of the 30th international Design Automation Conference
High level VLSI synthesis for multichip designs
High level VLSI synthesis for multichip designs
DSS: A Distributed High-Level Synthesis System
IEEE Design & Test
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Optimal temporal partitioning and synthesis for reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe
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In this paper we address the problem of partitioning register level designs for implementation on multiple FPGAs. The partitioner uses a modified multi-way Fiduccia-Mattheyses algorithm. Cost estimation functions needed by the partitioner to estimate the resources needed by the design on a FPGA have been developed. The methodology for estimation of resources on an FPGA (function generators, flip-flops and CLBs), and partitioning of the design are discussed in detail.