DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Net partitions yield better module partitions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
A quadratic metric with a simple solution scheme for initial placement
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A force-directed macro-cell placer
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
DSS: A Distributed High-Level Synthesis System
IEEE Design & Test
Facet: A procedure for the automated synthesis of digital systems
DAC '83 Proceedings of the 20th Design Automation Conference
| Hi-index | 0.02 |
Given an RTL (Register-Transfer-Level) netlist, a net dependency graph with weighted edges is built. Each node in the graph represents a net and an edge exists between two nodes if the two nets represented by the nodes share one or more macrocells. Clusters of nets are then formed by clique partitioning. A net cluster level floorplan is derived by simulated annealing to define the regions where the nets in each cluster must be routed. The macrocell placement is formulated as a force-directed problem where the terminals of a net are free to move under the influence of forces in the quest for optimal length of the net. A new type of rejection force is introduced in order to obtain a feasible placement. In comparison with the placements generated by CADENCE Silicon Ensemble, we obtained an average total wire length reduction of 22.8% and an average longest wire length reduction of 33% with an average area penalty of only 1.1%.