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Journal of the ACM (JACM)
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Algorithm 457: finding all cliques of an undirected graph
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The modeling and synthesis of bus systems
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HAL: A multi-paradigm approach to automatic data path synthesis
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Move frame scheduling and mixed scheduling-allocation for the automated synthesis of digital systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A neural network based algorithm for the scheduling problem in high-level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
EURO-DAC '94 Proceedings of the conference on European design automation
A multiple clocking scheme for low power RTL design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
False path exclusion in delay analysis of RTL-based datapath-controller designs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
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ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
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DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
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ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Accounting for various register allocation schemes during post-synthesis verification of RTL designs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
An automated data path synthesizer for a canonic structure, implementable in VLSI
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A new synthesis for the MIMOLA software system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
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Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs
Formal Methods in System Design - Special issue on formal methods for computer-added design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
False path exclusion in delay analysis of RTL structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Formal Methods in System Design
Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems
IEEE Design & Test
Contribution of Compilation Techniques to the Synthesis of Dedicated VLIW Architectures
PACT '93 Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism
A method of automatic data path synthesis
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DAC '84 Proceedings of the 21st Design Automation Conference
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A Hierarchical Register Optimization Algorithm for Behavioral Synthesis
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Net Clustering Based Macrocell Placement
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Resource Allocation and Binding Approach for Low Leakage Power
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Matching system and component behaviour in MIMOLA synthesis tools
EURO-DAC '90 Proceedings of the conference on European design automation
Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-Cell Placement
Journal of VLSI Signal Processing Systems
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
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CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
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In the past decade significant effort has been devoted to the development of methodologies for design at the register-transfer level. However, effective and versatile procedures are still not available. This paper presents an efficient procedure for the automated synthesis of data paths at the register-transfer level. The procedure minimizes the numbers of storage elements, data operators, and interconnection units. In addition, the procedure has the capability of exploring alternatives in the design space. In some preliminary experiments the procedure produced designs nearly identical to commercially produced designs.