Scheduling and binding algorithms for high-level synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Splicer: a heuristic approach to connectivity binding
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A new synthesis for the MIMOLA software system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
Facet: A procedure for the automated synthesis of digital systems
DAC '83 Proceedings of the 20th Design Automation Conference
A Knowledge-Based System for Designing Testable VLSI Chips
IEEE Design & Test
Move frame scheduling and mixed scheduling-allocation for the automated synthesis of digital systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Relevant issues in high-level connectivity synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Distributed design-space exploration for high-level synthesis systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A neural network based algorithm for the scheduling problem in high-level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
SYNTEST: an environment for system-level design for test
EURO-DAC '92 Proceedings of the conference on European design automation
Utilization of multiport memories in data path synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
Generating several solutions for the scheduling problem in high-level synthesis
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Interconnection synthesis with geometric constraints
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Design of Testable Multipliers for Fixed-Width Data Paths
IEEE Transactions on Computers
A flexible datapath allocation method for architectural synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Temporal floorplanning using the three-dimensional transitive closure subGraph
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Compatibility path based binding algorithm for interconnect reduction in high level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
T-trees: A tree-based representation for temporal and three-dimensional floorplanning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A unified approach for scheduling and allocation
Integration, the VLSI Journal
EUC'07 Proceedings of the 2007 conference on Emerging direction in embedded and ubiquitous computing
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A new method for high level synthesis is reported whose basic feature is the tight interaction and coupling of the scheduling and allocation phases providing a global direction to synthesis. A linear program based allocation is proposed which uses multifunction ALU cost estimation, and iteratively drives a tree search for scheduling. A major contribution of this paper is a new interconnect optimization algorithm which is based on several interconnect transformations for multiplexer input collapsing and merging. Several other important synthesis aspects are included, e.g. register and interconnect bindings, operation chaining and operation multicycling. The method has been implemented in C on a Sun 3/60,