Integrated scheduling and binding: a synthesis approach for design space exploration
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Low power high level synthesis by increasing data correlation
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Battery-Driven Dynamic Power Management
IEEE Design & Test
High Level Synthesis for Peak Power Minimization Using ILP
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
A Heuristic for Clock Selection in High-Level Synthesis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Peak Power Minimization Through Datapath Scheduling
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Non-Ideal Battery Properties and Low Power Operation in Wearable Computing
ISWC '99 Proceedings of the 3rd IEEE International Symposium on Wearable Computers
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis
Proceedings of the conference on Design, automation and test in Europe
ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
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The cycle-by-cycle power differential determines the noise introduced due to inductive ground bounce. However, very few attentions are paid to minimize the cycle-by-cycle power differential in high-level synthesis stage. In this paper, we investigate the simultaneous application of operation scheduling and operation delay selection for minimizing the cycle-by-cycle power differential. An integer linear programming (ILP) approach is proposed to formally formulate this problem. Benchmark data consistently show that our approach can minimize the cycle-by-cycle power differential within an acceptable run time. Compared with previous work, the relative improvement of our approach achieves 44.8%.