Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis

Authors:
C. Chen;M. Sarrafzadeh
Affiliations:
Dept. of Electrical and Computer Eng., The University of Windsor, Ontario, CANADA;Computer Science Department, UCLA, Los Angeles
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2002

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Abstract

The design of application (-domain) specific instruction-setprocessors (ASIPs), optimized for code size, has traditionallybeen accompanied by the necessity to program assembly,at least for the performance critical parts of the application.The highly encoded instruction sets simply lackthe orthogonal structure present in e.g. VLIW processors,that allows efficient compilation. This lack of efficient compilationtools has also severely hampered the design spaceexploration of code-size efficient instruction sets, and correspondingly,their tuning to the application domain. In [13]a practical method is demonstrated to model a broad classof highly encoded instruction sets in terms of virtual resourceseasily interpreted by classic resource constrainedschedulers (such as the popular list-scheduling algorithm),thereby allowing efficient compilation with well understoodcompilation tools. In this paper we will demonstrate thesuitability of this model to also enable instruction set design(-space exploration) with a simple, well-understoodand proven method long used in the High-Level Synthesis(HLS) of ASICs. A small case study proves the practicalapplicability of the method.