A Heuristic for Clock Selection in High-Level Synthesis

Authors:
J. Ramanujam;Sandeep Deshpande;Jinpyo Hong;Mahmut Kandemir
Affiliations:
Department of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA;Department of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA;Department of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA;Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA
Venue:
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Year:
2002

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Abstract

Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or exact (and expensive) methods have been used for clock selection. This paper presents a novel heuristic approach for near-optimal clock selection for synthesis systems. This technique is based on critical paths in the dataflow graph. In addition, we introduce and exploit a new figure of merit called the activity factor to choose the best possible clock. Extensive experimental results show that the proposed technique is very fast and produces optimal solutions in a large number of cases; in those cases, where it is not optimal, we are off by just a few percent from optimal.