System clock estimation based on clock slack minimization
EURO-DAC '92 Proceedings of the conference on European design automation
Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
Task scheduling and voltage selection for energy minimization
Proceedings of the 39th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
High-Level Synthesis with Variable-Latency Components
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
A Heuristic for Clock Selection in High-Level Synthesis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Novel sizing algorithm for yield improvement under process variation in nanometer technology
Proceedings of the 41st annual Design Automation Conference
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Using Bounds
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An ILP Formulation for Reliability-Oriented High-Level Synthesis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A New Method for Design of Robust Digital Circuits
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Modern floorplanning based on fast simulated annealing
Proceedings of the 2005 international symposium on Physical design
Temperature-aware resource allocation and binding in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
Incremental exploration of the combined physical and behavioral design space
Proceedings of the 42nd annual Design Automation Conference
An efficient algorithm for statistical minimization of total power under timing yield constraints
Proceedings of the 42nd annual Design Automation Conference
Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips
Proceedings of the 42nd annual Design Automation Conference
Timing variation-aware high-level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Variability-driven module selection with joint design time optimization and post-silicon tuning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A variation aware high level synthesis framework
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Tolerating process variations in high-level synthesis using transparent latches
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Variation-aware resource sharing and binding in behavioral synthesis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Timing variation-aware task scheduling and binding for MPSoC
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A variation-tolerant scheduler for better than worst-case behavioral synthesis
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Timing variation-aware high-level synthesis considering accurate yield computation
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Scheduling and resource binding algorithm considering timing variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing variation-aware scheduling and resource binding in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Variation-aware layout-driven scheduling for performance yield optimization
Proceedings of the International Conference on Computer-Aided Design
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
Static statistical MPSoC power optimization by variation-aware task and communication scheduling
Microprocessors & Microsystems
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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Meeting timing constraint is one of the most important issues for modern design automation tools. This situation is exacerbated with the existence of process variation. Current high-level synthesis tools, performing task scheduling, resource allocation and binding, may result in unexpected performance discrepancy due to the ignorance of the impact of process variation, which requires a shift in the design paradigm, from today's deterministic design to statistical or probabilistic design. In this paper, we present a variation-aware performance yield-guaranteed high-level synthesis algorithm. The proposed approach integrates high-level synthesis and statistical static timing analysis into a simulated annealing engine to simultaneously explore solution space while meeting design objectives. Our results show that the area reduction is in the average of 14% when 95% performance yield is imposed with the same total completion time constraint.