An architectural co-synthesis algorithm for distributed, embedded computing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hierarchical algorithms for assessing probabilistic constraints on system performance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 6th international workshop on Hardware/software codesign
Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
Estimating probabilistic timing performance for real-time embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Task scheduling and voltage selection for energy minimization
Proceedings of the 39th annual Design Automation Conference
Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Parallel and Distributed Systems
Probabilistic performance guarantee for real-time tasks with varying computation times
RTAS '95 Proceedings of the Real-Time Technology and Applications Symposium
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Fast statistical timing analysis handling arbitrary delay correlations
Proceedings of the 41st annual Design Automation Conference
A methodology to improve timing yield in the presence of process variations
Proceedings of the 41st annual Design Automation Conference
Novel sizing algorithm for yield improvement under process variation in nanometer technology
Proceedings of the 41st annual Design Automation Conference
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient search space exploration for HW-SW partitioning
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Variability inspired implementation selection problem
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Guaranteeing performance yield in high-level synthesis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Non-linear statistical static timing analysis for non-Gaussian variation sources
Proceedings of the 44th annual Design Automation Conference
Timing variation-aware high-level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Variation-aware task allocation and scheduling for MPSoC
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Variability-driven module selection with joint design time optimization and post-silicon tuning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing analysis using bounds and selective enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance yield-driven task allocation and scheduling for MPSoCs under process variation
Proceedings of the 47th Design Automation Conference
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Low-power resource binding by postsilicon customization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Process-variation-aware mapping of best-effort and real-time streaming applications to MPSoCs
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
Static statistical MPSoC power optimization by variation-aware task and communication scheduling
Microprocessors & Microsystems
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This work addresses the new problem of timing variation-aware task scheduling and binding (TSB) for multiprocessor system-on-chip (MPSoC) architecture in the system-level design, where tasks have full flexibilities of resource (i.e., processor) sharing to meet the design constraints. With the timing variation of processors' clock speed, it has been observed that considering the effects of resource sharing on the resulting performance yield computation is critically important for accurate design space exploration and evaluation in the system-level design. Unfortunately previous statistical static timing analysis (SSTA) in the system-level has never considered resource sharing in computing the performance yield, or has overly simplified by employing the gate-level SSTAs. In this work, we overcome those limitations by proposing an effective SSTA technique called TSB-SSTA, which schedules and binds tasks to resources in the presence of resource sharing. We also propose a timing variation-aware (TV) framework, called TSB-TV, tightly integrating TSB-SSTA. We have tested the effectiveness of our approach through experimentation with benchmarks, which showed an average of 56.1% improvement in performance yield over conventional methods.