A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning
EURO-DAC '94 Proceedings of the conference on European design automation
Incremental hardware estimation during hardware/software functional partitioning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A hardware/software partitioner using a dynamically determined granularity
DAC '97 Proceedings of the 34th annual Design Automation Conference
Proceedings of the 6th international workshop on Hardware/software codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HW / SW partitioning approach for reconfigurable system design
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
On the hardware-software partitioning problem: System modeling and partitioning techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Clock-frequency assignment for multiple clock domain systems-on-a-chip
Proceedings of the conference on Design, automation and test in Europe
Computers and Electrical Engineering
Timing variation-aware task scheduling and binding for MPSoC
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
PDCS '07 Proceedings of the 19th IASTED International Conference on Parallel and Distributed Computing and Systems
Partitioning and scheduling of task graphs on partially dynamically reconfigurable FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification
Journal of Signal Processing Systems
A polynomial algorithm for partitioning problems
ACM Transactions on Embedded Computing Systems (TECS)
Server-side coprocessor updating for mobile devices with FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Concept-based partitioning for large multidomain multifunctional embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A hybrid heuristic algorithm for HW-SW partitioning within timed automata
KES'06 Proceedings of the 10th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part I
Architecture-driven reliability optimization with uncertain model parameters
Journal of Systems and Software
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Hardware/software (HW-SW) partitioning is a key problem in the codesign of embedded systems, studied extensively in the past. One major open challenge for traditional partitioning approaches -- as we move to more complex and heterogeneous SOCs -- is the lack of efficient exploration of the large space of possible HW/SW configurations, coupled with the inability to efficiently scale up with larger problem sizes. In this paper, we make two contributions for HW-SW partitioning of applications represented as procedural call-graphs: 1) we prove that during partitioning, the execution time metric for moving a vertex needs to be updated only for the immediate neighbours of the vertex, rather than for all ancestors along paths to the root vertex; consequently, we observe faster run-times for move-based partitioning algorithms such as Simulated Annealing (SA), allowing call graphs with thousands of vertices to be processed in less than a second, and 2) we devise a new cost function for SA that allows frequent discovery of better partitioning solutions by searching spaces overlooked by traditional SA cost functions. We present experimental results on a very large design space, where several thousand configurations are explored in minutes as compared to several hours or days using a traditional SA formulation. Furthermore, our approach is frequently able to locate better design points with over 10% improvement in application execution time compared to the solutions generated by a Kernighan-Lin partitioning algorithm starting with an all-SW partitioning.