Partitioning and scheduling of task graphs on partially dynamically reconfigurable FPGAs

Authors:
Roberto Cordone;Francesco Redaelli;Massimo Antonio Redaelli;Marco Domenico Santambrogio;Donatella Sciuto
Affiliations:
Dipartimento di Tecnologie dell'Informazione, Università degli Studi di Milano, Crema, Italy;Microarchitecture Laboratory, Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy;Microarchitecture Laboratory, Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy;Microarchitecture Laboratory, Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy;Microarchitecture Laboratory, Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2009

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Abstract

This paper proposes a new model for the partitioning and scheduling of a specification on partially dynamically reconfigurable hardware. Although this problem can be solved optimally only by tackling its subproblems jointly, the exceeding complexity of such a task leads to a decomposition into two phases. The partitioning phase is based on a new graph-theoretic approach, which aims to obtain near optimality even if performed independently from the subsequent phase. For the scheduling phase, a new integer linear programming formulation and a heuristic approach are developed. Both take into account configuration prefetching and module reuse. The experimental results show that the proposed method compares favorably with existing solutions.