Modern heuristic techniques for combinatorial problems
Modern heuristic techniques for combinatorial problems
Scheduling with bus access optimization for distributed embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Computers and Intractability; A Guide to the Theory of NP-Completeness
Computers and Intractability; A Guide to the Theory of NP-Completeness
Designing fault tolerant systems into SRAM-based FPGAs
Proceedings of the 40th annual Design Automation Conference
The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the 42nd annual Design Automation Conference
Towards a Dependable Component Technology for Embedded System Applications
WORDS '05 Proceedings of the 10th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems
Software-controlled fault tolerance
ACM Transactions on Architecture and Code Optimization (TACO)
Application-Based Metrics for Strategic Placement of Detectors
PRDC '05 Proceedings of the 11th Pacific Rim International Symposium on Dependable Computing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Cost-efficient soft error protection for embedded microprocessors
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Online task-scheduling for fault-tolerant low-energy real-time systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Software and Hardware Techniques for SEU Detection in IP Processors
Journal of Electronic Testing: Theory and Applications
Compiler-assisted soft error detection under performance and energy constraints in embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Partitioning and scheduling of task graphs on partially dynamically reconfigurable FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Dependable and Secure Computing
Performance optimization of error detection based on speculative reconfiguration
Proceedings of the 48th Design Automation Conference
Towards fault-tolerant embedded systems with imperfect fault detection
Proceedings of the 49th Annual Design Automation Conference
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant real-time distributed embedded systems used for safety-critical applications. An application is modeled as a set of processes communicating by messages. Processes are mapped on computation nodes connected to the communication infrastructure. To provide resiliency against transient faults, efficient error detection and recovery techniques have to be employed. Our main focus in this paper is on the efficient implementation of the error detection mechanisms. We have developed techniques to optimize the hardware/software implementation of error detection, in order to minimize the global worst-case schedule length, while meeting the imposed hardware cost constraints and tolerating multiple transient faults. We present two design optimization algorithms which are able to find feasible solutions given a limited amount of resources: the first one assumes that, when implemented in hardware, error detection is deployed on static reconfigurable FPGAs, while the second one considers partial dynamic reconfiguration capabilities of the FPGAs.