Floorplacement for partial reconfigurable FPGA-based systems

Authors:
A. Montone;M. D. Santambrogio;F. Redaelli;D. Sciuto
Affiliations:
Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy;Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy and Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, Cambridge, MA;Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy;Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy
Venue:
International Journal of Reconfigurable Computing - Special issue on selected papers from the 17th reconfigurable architectures workshop (RAW2010)
Year:
2011

Citing 12
Cited 1

DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems

FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems

RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
Temporal floorplanning using the T-tree formulation

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Unification of partitioning, placement and floorplanning

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Heterogeneous Floorplanning for FPGAs

VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Temporal floorplanning using the three-dimensional transitive closure subGraph

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Task scheduling with configuration prefetching and anti-fragmentation techniques on dynamically reconfigurable systems

Proceedings of the conference on Design, automation and test in Europe
A Reconfiguration-Aware Floorplacer for FPGAs

RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
Partitioning and scheduling of task graphs on partially dynamically reconfigurable FPGAs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fixed-outline floorplanning: enabling hierarchical design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI module placement based on rectangle-packing by the sequence-pair

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Min-cut floorplacement

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Design space exploration for partially reconfigurable architectures in real-time systems

Journal of Systems Architecture: the EUROMICRO Journal

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Abstract

We presented a resource- and configuration-aware floorplacement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, using an objective function based on external wirelength. Our work aims at identifying groups of Reconfigurable Functional Units that are likely to be configured in the same chip area, identifying these areas based on resource requirements, device capabilities, and wirelength. Task graphs with few externally connected RRs lead to the biggest decrease, while external wirelength in task graphs with many externally connected RRs show lower improvement. The proposed approach results, as also demonstrated in the experimental results section, in a shorter external wirelength (an average reduction of 50%) with respect to purely area-driven approaches and a highly increased probability of reuse of existing links (90% reduction can be obtained in the best case).