ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Seeing the forest and the trees: Steiner wirelength optimization in placemen
Proceedings of the 2006 international symposium on Physical design
Solving hard instances of floorplacement
Proceedings of the 2006 international symposium on Physical design
Satisfying whitespace requirements in top-down placement
Proceedings of the 2006 international symposium on Physical design
Improved timing closure by early buffer planning in floor-placement design flow
Proceedings of the 17th ACM Great Lakes symposium on VLSI
An effective buffer planning algorithm for IP based fixed-outline SOC placement
Proceedings of the 17th ACM Great Lakes symposium on VLSI
RQL: global placement via relaxed quadratic spreading and linearization
Proceedings of the 44th annual Design Automation Conference
NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
DPlace2.0: a stable and efficient analytical placement based on diffusion
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A novel performance driven power gating based on distributed sleep transistor network
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Constraint-driven floorplan repair
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Solving modern mixed-size placement instances
Integration, the VLSI Journal
Signal skew aware floorplanning and bumper signal assignment technique for flip-chip
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Handling complexities in modern large-scale mixed-size placement
Proceedings of the 46th Annual Design Automation Conference
Fast unified floorplan topology generation and sizing on heterogeneous FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decoupling capacitance efficient placement for reducing transient power supply noise
Proceedings of the 2009 International Conference on Computer-Aided Design
SafeChoice: a novel clustering algorithm for wirelength-driven placement
Proceedings of the 19th international symposium on Physical design
DeFer: deferred decision making enabled fixed-outline floorplanning algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Placement and Floorplanning in Dynamically Reconfigurable FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Exploiting local logic structures to optimize multi-core SoC floorplanning
Proceedings of the Conference on Design, Automation and Test in Europe
A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
Integration, the VLSI Journal
Quantifying academic placer performance on custom designs
Proceedings of the 2011 international symposium on Physical design
Buffer planning for IP placement using sliced-LFF
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Floorplacement for partial reconfigurable FPGA-based systems
International Journal of Reconfigurable Computing - Special issue on selected papers from the 17th reconfigurable architectures workshop (RAW2010)
Re-synthesis for cost-efficient circuit-level timing speculation
Proceedings of the 48th Design Automation Conference
A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Towards layout-friendly high-level synthesis
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Statistical full-chip total power estimation considering spatially correlated process variations
Integration, the VLSI Journal
Hierarchical congregated ant system for bottom-up VLSI placements
Engineering Applications of Artificial Intelligence
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
VLSI floorplanning based on the integration of adaptive search models
Journal of Computer and Systems Sciences International
CusNoC: fast full-chip custom NoC generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Large macro blocks, predesigned datapaths, embedded memories, and analog blocks are increasingly used in application-specific integrated circuit (ASIC) designs. However, robust algorithms for large-scale placement of such designs have only recently been considered in the literature. Large macros can be handled by traditional floorplanning, but are harder to account for in min-cut and analytical placement. On the other hand, traditional floorplanning techniques do not scale to large numbers of objects, especially in terms of solution quality. The authors propose to integrate min-cut placement with fixed-outline floorplanning to solve the more general placement problem, which includes cell placement, floorplanning, mixed-size placement, and achieving routability. At every step of min-cut placement, either partitioning or wirelength-driven fixed-outline floorplanning is invoked. If the latter fails, the authors undo an earlier partitioning decision, merge adjacent placement regions, and refloorplan the larger region to find a legal placement for the macros. Empirically, this framework improves the scalability and quality of results for traditional wirelength-driven floorplanning. It has been validated on recent designs with embedded memories and accounts for routability. Additionally, the authors propose that free-shape rectilinear floorplanning can be used with rough module-area estimates before logic synthesis