Optimal orientations of cells in slicing floorplan designs
Information and Control
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Divide-and-conquer approximation algorithms via spreading metrics
Journal of the ACM (JACM)
Fast placement approaches for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Introduction to VLSI Physical Design
An Introduction to VLSI Physical Design
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
DAC '82 Proceedings of the 19th Design Automation Conference
Multi-Million Gate FPGA Physical Design Challenges
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Floorplan design for multi-million gate FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Heterogeneous Floorplanning for FPGAs
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
LFF algorithm for heterogeneous FPGA floorplanning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Computational Geometry: Algorithms and Applications
Computational Geometry: Algorithms and Applications
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A unified approach to topology generation and optimal sizing of floorplans
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Constrained floorplanning using network flows
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing-driven partitioning-based placement for island style FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Floorplan Design for Multimillion Gate FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
VLSI floorplanning based on the integration of adaptive search models
Journal of Computer and Systems Sciences International
ReShape: Towards a High-Level Approach to Design and Operation of Modular Reconfigurable Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
| Hi-index | 0.03 |
Recent field-programmable gate array (FPGA) architectures are heterogeneous, owing to the presence of millions of gates in configurable logic blocks (CLBs), block RAMs, and multiplier blocks (MULs) which can host fairly large designs. While their physical design calls for floorplanning, the traditional algorithms for application-specific integrated circuits (ASIC) do not suffice. In this paper, we propose a three-phase algorithm for unified floorplan-topology generation and sizing on heterogeneous FPGAs. The method consists of a recursive balanced bipartitioning followed by the generation of slicing topologies and finally the allocation of CLBs and RAM/MULs to modules by a greedy heuristic and minimum-cost maximum-flow method, respectively. Experimental results on benchmark circuits show that our method HeteroFloorplan produces feasible floorplans within a few seconds with total half-perimeter wirelength (HPWL) improvement of 18%-52% over the very few previous approaches. We also compare our locally greedy CLB allocation with a network-flow formulation to establish its effectiveness.