Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Fast unified floorplan topology generation and sizing on heterogeneous FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Placement and Floorplanning in Dynamically Reconfigurable FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Floorplacement for partial reconfigurable FPGA-based systems
International Journal of Reconfigurable Computing - Special issue on selected papers from the 17th reconfigurable architectures workshop (RAW2010)
Architecture-Aware reconfiguration-centric floorplanning for partial reconfiguration
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
ReShape: Towards a High-Level Approach to Design and Operation of Modular Reconfigurable Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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The large size of modern FPGAs has caused researchers to consider deploying hierarchical techniques in their design. In this paper, we consider the floorplanning of FPGAs. We present a two-step approach for the floorplanning of modern FPGAs that we believe is cleaner and more versatile than recent floorplanners. The steps, based on resource-aware fixed outline simulated annealing and constrained floorplanning, are adapted to address the heterogeneous nature of FPGA floorplanning. Experiments demonstrate the viability of our approach.