Strategic directions in real-time and embedded systems
ACM Computing Surveys (CSUR) - Special ACM 50th-anniversary issue: strategic directions in computing research
Optimal FPGA module placement with temporal precedence constraints
Proceedings of the conference on Design, automation and test in Europe
Co-Synthesis of Hardware and Software for Digital Embedded Systems
Co-Synthesis of Hardware and Software for Digital Embedded Systems
VISI Physical Design Automation: Theory and Practice
VISI Physical Design Automation: Theory and Practice
DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Temporal floorplanning using the T-tree formulation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Unification of partitioning, placement and floorplanning
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Heterogeneous Floorplanning for FPGAs
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Temporal floorplanning using the three-dimensional transitive closure subGraph
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Architecture-Aware reconfiguration-centric floorplanning for partial reconfiguration
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
On the Evolution of Hardware Circuits via Reconfigurable Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Automatic floorplanning and interface synthesis of island style reconfigurable systems with GOAHEAD
ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems
ReShape: Towards a High-Level Approach to Design and Operation of Modular Reconfigurable Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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The aim of this article is to describe a complete partitioning and floorplanning algorithm tailored for reconfigurable architectures deployable on FPGAs and considering communication infrastructure feasibility. This article proposes a novel approach for resource- and reconfiguration- aware floorplanning. Different from existing approaches, our floorplanning algorithm takes specific physical constraints such as resource distribution and the granularity of reconfiguration possible for a given FPGA device into account. Due to the introduction of constraints typical of other problems like partitioning and placement, the proposed approach is named floorplacer in order to underline the great differences with respect to traditional floorplanners. These physical constraints are typically considered at the later placement stage. Different aspects of the problems have been described, focusing particularly on the FPGAs resource heterogeneity and the temporal dimension typical of reconfigurable systems. Once the problem is introduced a comparison among related works has been provided and their limits have been pointed out. Experimental results proved the validity of the proposed approach.