FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Configuration Caching and Swapping
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Configuration Compression for the Xilinx XC6200 FPGA
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs
Proceedings of the 3rd conference on Computing frontiers
Modeling and design of fault-tolerant and self-adaptive reconfigurable networked embedded systems
EURASIP Journal on Embedded Systems
The shining embedded system design methodology based on self dynamic reconfigurable architectures
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A multilayer framework supporting autonomous run-time partial reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Zero logic overhead integration of partially reconfigurable modules
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Placement and Floorplanning in Dynamically Reconfigurable FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Dedicated module access in dynamically reconfigurable systems
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Internal and external bitstream relocation for partial dynamic reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mechanism of resource virtualization in RCS for multitask stream applications
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
A cost model for partial dynamic reconfiguration
Transactions on High-Performance Embedded Architectures and Compilers IV
HTR: on-chip hardware task relocation for partially reconfigurable FPGAs
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
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The feature of partial reconfiguration provided by currently available Field Programmable Gate Arrays (FPGAs) makes it possible to change hardware modules while others keep working. The combination of this feature and the high gate capacity enables the integration of dynamic systems that can be adapted to changing demands during runtime. Placing the dynamically changing modules along a horizontal communication infrastructure does not only provide communication facilities it also enables the relocation of pre-synthesized modules by bitstream manipulations. The exact placement of an incoming module is determined according to the current resource allocation, which results in an online placement problem. In order to prevent any extra configuration overhead for the relocation process, we developed the REPLICA (Relocation per online Configuration Alteration) filter, which is capable of performing the necessary bitstream manipulations during the regular download process. The filter architecture, a Configuration Manager and an evaluation example are presented in this paper.