A study of permutation crossover operators on the traveling salesman problem
Proceedings of the Second International Conference on Genetic Algorithms on Genetic algorithms and their application
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Proceedings of the 39th annual Design Automation Conference
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
The Intrinsic Evolution of Virtex Devices Through Internet Reconfigurable Logic
ICES '00 Proceedings of the Third International Conference on Evolvable Systems: From Biology to Hardware
AllelesLociand the Traveling Salesman Problem
Proceedings of the 1st International Conference on Genetic Algorithms
The Impact of Technology Scaling on Lifetime Reliability
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Evolutionary functional recovery in virtual reconfigurable circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A multilayer framework supporting autonomous run-time partial reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Applying adaptive algorithms to epistatic domains
IJCAI'85 Proceedings of the 9th international joint conference on Artificial intelligence - Volume 1
Virtual reconfigurable circuits for real-world applications of evolvable hardware
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
A flexible on-chip evolution system implemented on a xilinx Virtex-II pro device
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
Fault Classification for SRAM-Based FPGAs in the Space Environment for Fault Mitigation
IEEE Embedded Systems Letters
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A hardware/software platform for intrinsic evolvable hardware is designed and evaluated for digital circuit design and repair on Xilinx Field Programmable Gate Arrays (FPGAs). Dynamic bitstream compilation for mutation and crossover operators is achieved by directly manipulating the bitstream using a layered framework. Experimental results on a case study have shown that benchmark circuit evolution from an unseeded initial population, as well as a complete recovery of a stuck-at fault is achievable using this platform. An average of 0.47@ms is required to perform the genetic mutation, 4.2@ms to perform the single point conventional crossover, 3.1@ms to perform Partial Match Crossover (PMX) as well as Order Crossover (OX), 2.8@ms to perform Cycle Crossover (CX), and 1.1ms for one input pattern intrinsic evaluation. These represent a performance advantage of three orders of magnitude over the JBITS software framework and more than seven orders of magnitude over the Xilinx design tool driven flow for realizing intrinsic genetic operators on Xilinx Virtex Family devices.