The Total Delay Fault Model and Statistical Delay Fault Coverage
IEEE Transactions on Computers
A Statistical Model for Delay-Fault Testing
IEEE Design & Test
A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity Memories
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Multiple-output propagation transition fault test
Proceedings of the IEEE International Test Conference 2001
On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Scan-Based Transition Fault Testing " Implementation and Low Cost Test Challenges
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Static electromigration analysis for on-chip signal interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Online diagnosis of hard faults in microprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
Hi-index | 0.00 |
As device sizes shrink and current densities increase, the probability of device failures due to gate oxide breakdown (OBD) also increases. To provide designs that are tolerant to such failures, we must investigate and understand the manifestations of this physical phenomenon at the circuit and system level. In this paper, we develop a model for operational OBD defects, and we explore how to test for faults due to OBD. For a NAND gate, we derive the necessary input conditions that excite and detect errors due to OBD defects at the gate level. We show that traditional pattern generators fail to exercise all of these defects. Finally, we show that these test patterns can be propagated and justified for a combinational circuit in a manner similar to traditional ATPG.