REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Optimal Free-Space Management and Routing-Conscious Dynamic Placement for Reconfigurable Devices
IEEE Transactions on Computers
Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration
FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
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IEICE - Transactions on Information and Systems
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ICA3PP'12 Proceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
HTR: on-chip hardware task relocation for partially reconfigurable FPGAs
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
International Journal of Reconfigurable Computing
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The research described in this paper shows how the runtime relocation of a reconfigurable component can be obtained using a system component that is able to update the bitstream information, moving the reconfigurable module in the desired position. This scenario defines the so-called partial bitstream relocation activity. This paper proposes a relocation filter that can be implemented both as a hardware and a software component. The former is hosted in the static part of the reconfigurable architecture, while the latter is made to be run on the processor placed on the field-programmable gate array (FPGA). The proposed approach has also been validated over different FPGAs, i.e., Virtex II Pro, Virtex 4, and Virtex 5, proposing a runtime relocation support that can be customized to meet all the different constraints associated with these different target architectures.