Secure processing using dynamic partial reconfiguration
Proceedings of the 5th Annual Workshop on Cyber Security and Information Intelligence Research: Cyber Security and Information Intelligence Challenges and Strategies
Design optimizations to improve placeability of partial reconfiguration modules
Proceedings of the Conference on Design, Automation and Test in Europe
Internal and external bitstream relocation for partial dynamic reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mechanism of resource virtualization in RCS for multitask stream applications
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
Energy reduction by systematic run-time reconfigurable hardware deactivation
Transactions on High-Performance Embedded Architectures and Compilers IV
Dynamic Defragmentation of Reconfigurable Devices
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A bitstream relocation technique to improve flexibility of partial reconfiguration
ICA3PP'12 Proceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
HTR: on-chip hardware task relocation for partially reconfigurable FPGAs
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
A Fault Tolerant Approach for FPGA Embedded Processors Based on Runtime Partial Reconfiguration
Journal of Electronic Testing: Theory and Applications
International Journal of Reconfigurable Computing
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This paper introduces a method that enhances the relocatability of partial bitstreams for FPGA run-time reconfiguration. Reconfigurable applications usually employ partial bitstreams which are specific to one target region on the FPGA. Previously, techniques have been proposed that allow relocation between identical regions on the FPGA. However, as FPGAs are becoming increasingly heterogeneous, this approach is often too restrictive. We introduce a method that circumvents the problem of having to find fully identical regions based on compatible subsets of resources, enabling flexible placement of relocatable modules. In a software defined radio prototype with two reconfigurable regions, the number of partial bitstreams is reduced by 50% and the compile time is shortened by 43%.