Efficiently supporting fault-tolerance in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Platform Based on Open-Source Cores for Industrial Applications
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Reconfigurable Architecture for Autonomous Self-Repair
IEEE Design & Test
The Impact of Technology Scaling on Lifetime Reliability
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Designing Fault-Tolerant Techniques for SRAM-Based FPGAs
IEEE Design & Test
Column-Based Precompiled Configuration Techniques for FPGA
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Configuration bitstream compression for dynamically reconfigurable FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A Secure Self-Reconfiguring Architecture Based on Open-Source Hardware
RECONFIG '05 Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) on Reconfigurable Computing and FPGAs
Proceedings of the 43rd annual Design Automation Conference
Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration
FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Toward Increasing FPGA Lifetime
IEEE Transactions on Dependable and Secure Computing
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
A low-cost SEE mitigation solution for soft-processors embedded in systems on programmable chips
Proceedings of the Conference on Design, Automation and Test in Europe
Progress in autonomous fault recovery of field programmable gate arrays
ACM Computing Surveys (CSUR)
A Novel Design Methodology for Implementing Reliability-Aware Systems on SRAM-Based FPGAs
IEEE Transactions on Computers
A lean FPGA soft processor built using a DSP block
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Portable, flexible, and scalable soft vector processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The ever increasing adoption of field programmable devices in various application domains for building complex embedded systems based on FPGA processors along with the reliability issues having emerged for FPGA devices built with the latest nanometer technologies, have raised the need for new fault tolerant techniques in order to improve dependability and extend system lifetime. In addition, the runtime partial reconfiguration technology highly mature in the modern FPGA families along with the availability of unused programmable resources in most FPGA designs provide new and interesting opportunities to build advanced fault tolerance mechanisms. In this paper, we exploit the dynamic reconfiguration potential of today's FPGA architectures and the advances in the related design support tools and we propose a fault-tolerant approach for FPGA embedded processors based on runtime partial reconfiguration. According to the proposed methodology, the processor core is partitioned into reconfigurable modules and each module is duplicated to implement a concurrent error detection mechanism. Precompiled configurations containing spare resources are generated for each duplicated module and are used to repair at runtime the defective modules. Also, a fault tolerance scheme for the proxy logic of the reconfigurable modules, which cannot move in the alternative configurations along with the rest logic, is proposed. Moreover, a compression method for the alternative partial bitstreams, which significantly reduces the high storage space requirements of the proposed approach, is presented. Two different hardware decompression schemes have been implemented in a Virtex-5 device and compared in terms of area overhead and decompression latency. Furthermore, a thorough examination has been performed, regarding how the percentage of the spare resources and their allocation in the reconfigurable regions affect the compression efficiency and the processor performance. Finally, the proposed approach has been demonstrated in three different components --- ALU, multiplier-accumulator, and instruction-fetch unit --- of an open-source embedded processor.