The design of an SRAM-based field-programmable gate array—part I: architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Asynchronous circuits transient faults sensitivity evaluation
Proceedings of the 42nd annual Design Automation Conference
A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs
IEEE Transactions on Computers
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic
IEEE Transactions on Computers
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs
Journal of Electronic Testing: Theory and Applications
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Microprocessors & Microsystems
Reliability and availability in reconfigurable computing: a basis for a common solution
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
A Fault Tolerant Approach for FPGA Embedded Processors Based on Runtime Partial Reconfiguration
Journal of Electronic Testing: Theory and Applications
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This paper analyses the effects of Single Event Upsets in an SRAM-based FPGA, with special emphasis for the transient faults affecting the configuration memory. Two approaches are combined: from one side, by exploiting the available information and tools dealing with the device configuration memory, we were able to make hypothesis on the meaning of every bit in the configuration memory. From the other side, radiation testing was exploited to validate the hypothesis and to gather experimental evidence about the correctness of the obtained results. As a major result, we can provide detailed information about the effects of SEUs affecting the configuration memory of a commercial FPGA device. As a second contribution, we describe a method for obtaining the same result with similar devices. Finally, the obtained results are crucial to allow the possible usage of SRAM-based FPGAs in safety-critical environments, e.g., by working on the place and route strategies of the supporting tools.