Asynchronous circuits and systems: a promising design alternative
Proceedings of MIGAS fourth session on Microelectronics for telecommunications : managing high complexity and mobility: managing high complexity and mobility
Differential Fault Analysis of Secret Key Cryptosystems
CRYPTO '97 Proceedings of the 17th Annual International Cryptology Conference on Advances in Cryptology
New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments
Journal of Electronic Testing: Theory and Applications
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Asynchronous Circuits Sensitivity to Fault Injection
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Hardening Techniques against Transient Faults for Asynchronous Circuits
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Design of asynchronous circuits for high soft error tolerance in deep submicrometer CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing robust threshold gates against soft errors
Microelectronics Journal
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This paper presents a transient faults sensitivity evaluation for Quasi Delay Insensitive (QDI) asynchronous circuits. Because of their specific architecture, asynchronous circuits have a very different behavior than synchronous circuits in the presence of faults. We address the effects of transient faults in QDI circuits and describe the causes that lead the faults to be memorized into one or more soft errors. Therefore, a refined fault sensitivity criterion is defined for this class of circuits. This methodology enables us to point out the weak parts of a circuit. An analysis tool is implemented to support this evaluation. This tool provides a quantitative study of the fault sensitivity, and enables us to compare the robustness of different architectures of a circuit along the steps of its design flow. The objective of this work is to evaluate the circuits robustness against natural faults (single fault model) and intentional fault injection (multiple faults model).