From Design Validation to Hardware Testing: A Unified Approach
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
A Fault Injection Technique for VHDL Behavioral-Level Models
IEEE Design & Test
Validating fault tolerant designs using laser fault injection (LFI)
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Fault Injection in VHDL Descriptions and Emulation
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
A Low-Cost Hardware Approach to Dependability Validation of Ips
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Comparison and Application of Different VHDL-Based Fault Injection Techniques
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
From Specification Validation to Hardware Testing: A Unified Method
Proceedings of the IEEE International Test Conference on Test and Design Validity
Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary Results
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Two Fault Injection Techniques for Test of Fault Handling Mechanisms
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
MEFISTO-L: A VHDL-Based Fault Injection Tool for the Experimental Assessment of Fault Tolerance
FTCS '98 Proceedings of the The Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing
Optimized Generation of VHDL Mutants for Injection of Transition Errors
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
New Techniques for Accelerating Fault Injection in VHDL Descriptions
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Bit Flip Injection in Processor-Based Architectures: A Case Study
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Fault Tolerance Evaluation Using Two Software Based Fault Injection Methods
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Fault Tolerant Insertion and Verification: A Case Study
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
FPGA-Based Fault Injection for Microprocessor Systems
ATS '01 Proceedings of the 10th Asian Test Symposium
Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance
Proceedings of the conference on Design, automation and test in Europe
New Techniques for Speeding-Up Fault-Injection Campaigns
Proceedings of the conference on Design, automation and test in Europe
Emulating static faults using a Xilinx based emulator
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Exploiting FPGA for Accelerating Fault Injection Experiments
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Supporting Fault Tolerance in an Industrial Environment: The AMATISTA Approach
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Logic synthesis of multilevel circuits with concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault emulation: A new methodology for fault grading
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Asynchronous circuits transient faults sensitivity evaluation
Proceedings of the 42nd annual Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic
IEEE Transactions on Computers
Early Analysis of Fault-based Attack Effects in Secure Circuits
IEEE Transactions on Computers
ACL2 for the verification of fault-tolerance properties: first results
Proceedings of the Eighth International Workshop on the ACL2 Theorem Prover and its Applications
Statistical fault injection: quantified error and confidence
Proceedings of the Conference on Design, Automation and Test in Europe
Towards robustness analysis using PVS
ITP'11 Proceedings of the Second international conference on Interactive theorem proving
Feasibility analysis for robustness quantification by symbolic model checking
Formal Methods in System Design
POWER-MODES: POWer-EmulatoR- and MOdel-Based DEpendability and Security Evaluations
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
| Hi-index | 0.01 |
The probability of transient faults increases with the evolution of technologies. There is a corresponding increased demand for an early analysis of erroneous behaviours. This paper discusses alternative approaches to perform transient fault injection in circuits described in a high level language such as VHDL. In the proposed analysis flow, a behavioural model is generated, allowing the designer to identify the detailed error propagation paths in the circuit. This paper also reports on results obtained with SEU-like fault injections in VHDL descriptions of digital circuits. Several circuit description levels are considered, as well as several fault modelling levels. These results show that an analysis performed at a very early stage in the design process can actually give a helpful insight into the response of a circuit when a fault occurs.