An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits
Journal of Electronic Testing: Theory and Applications
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Proceedings of the 40th annual Design Automation Conference
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments
Journal of Electronic Testing: Theory and Applications
SystemC
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation
Journal of Electronic Testing: Theory and Applications
Emulating switch-level models of CMOS circuits
Microelectronic Engineering
Fast co-verification of HDL models
Microelectronic Engineering
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware
Journal of Electronic Testing: Theory and Applications
Fault emulation for dependability evaluation of VLSI systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Switch-level soft error emulation for SET-induced pulses of variable strengths
Microelectronics Journal
Fast run-time reconfiguration for SEU injection
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
SCFIT: a FPGA-based fault injection technique for SEU fault model
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we introduce a method that uses the field programmable gate array (FPGA)-based emulation system for fault grading. The real-time simulation capability of a hardware emulator could significantly improve the performance of fault grading, which is one of the most time consuming tasks in the circuit design and test process. We employ a serial fault emulation algorithm enhanced by two speed-up techniques. First, a set of independent faults can be injected and emulated at the same time. Second, multiple dependent faults can be simultaneously injected within a single FPGA-configuration by adding extra circuitry. Because the reconfiguration time of mapping the numerous faulty circuits into the FPGA's is pure overhead and could be the bottleneck of the entire process, using extra circuitry for injecting a large number of faults can reduce the number of FPGA-reconfigurations and, thus, improving the performance significantly. In addition, we address the issue of handling potentially detected faults in this hardware emulation environment by using the dual-railed logic. The performance estimation shows that this approach could be several orders of magnitude faster than the existing software approaches for large sequential designs