Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
FPGA-Based Fault Injection into Synthesizable Verilog HDL Models
SSIRI '08 Proceedings of the 2008 Second International Conference on Secure System Integration and Reliability Improvement
Sequential circuit fault simulation using logic emulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault emulation: A new methodology for fault grading
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A layout-based approach for multiple event transient analysis
Proceedings of the 50th Annual Design Automation Conference
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In this paper, we have proposed a fast and easy-to-develop FPGA-based fault injection technique. This technique uses the Altera FPGAs debugging facilities in order to inject SEU fault model in both flip-flops and memory units. Since this method uses the FPGAs built-in facilities, it imposes a negligible performance and area overhead on the system. The experimental results on Leon2 processor shows that the proposed technique is on average four orders of magnitude faster than a simulation-based fault injection.