An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits
Journal of Electronic Testing: Theory and Applications
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Dynamic Delay-Fault Injection for Reconfigurable Hardware
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 16 - Volume 17
Emulating switch-level models of CMOS circuits
Microelectronic Engineering
Fast co-verification of HDL models
Microelectronic Engineering
Fault emulation for dependability evaluation of VLSI systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fault insertion testing of a novel CPLD-based fail-safe system
Proceedings of the Conference on Design, Automation and Test in Europe
Fast run-time reconfiguration for SEU injection
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
SCFIT: a FPGA-based fault injection technique for SEU fault model
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Hi-index | 0.03 |
A fast fault simulation approach based on ordinary logic emulation is proposed. The circuit configured into our system that emulates the faulty circuit's behaviour is synthesized from the good circuit and the given fault list in a novel way. Fault injection is made easy by shifting the content of a fault injection scan chain or by selecting the output of a parallel fault injection selector, with which we get rid of the time-consuming bit-stream regeneration process. Experimental results for ISCAS-89 benchmark circuits show that our serial fault emulator is about 20 times faster than HOPE. The speedup grows with the circuit size by our analysis. Two hybrid fault emulation approaches are also proposed. The first reduces the number of faults actually emulated by screening off faults not activated or with short propagation distances before emulation, and by collapsing nonstem faults into their equivalent stem faults. The second reduces the hardware requirement of the fault emulator by incorporating an ordinary fault simulator