An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits
Journal of Electronic Testing: Theory and Applications
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
The Java environment for reconfigurable computing
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Simulating Static and Dynamic Faults in BIST Strucutres with a FPGA Based Emulator
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Fault simulation on reconfigurable hardware
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Sequential circuit fault simulation using logic emulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dependability metrics
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Modern internet and telephone switches consist of numerous VLSI-circuits operating at high frequencies to handle high bandwidths. It is beyond question that such systems must contain mechanisms making them reliable through fault-detection or fault-tolerance. For monetary reasons, one or multiple Field Programmable Gate Arrays (FPGAs) are used in modern Application Specific Integrated Circuit (ASIC) development systems before production. Hardware manufacturers have a strong focus on quick fault-injection to verify and validate the correct function of such a (faulttolerant) system. However, current FPGA-based fault injection schemes do not consider delay faults. In this paper we present an extension to traditional FPGA fault injection schemes without any additional hardware for fixed and small hardware overhead for dynamic phase shifting. By using digital clock managers (DCMs), we are able to inject delay faults very fast through phase-shift variation of the clock without reconfiguring the FPGA.