Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Hardware emulation for functional verification of K5
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Efficient modeling of switch-level networks containing undetermined logic node states
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A switch level fault simulation environment
Proceedings of the 37th Annual Design Automation Conference
Automated equivalence checking of switch level circuits
Proceedings of the 39th annual Design Automation Conference
FOCUS: An Experimental Environment for Fault Sensitivity Analysis
IEEE Transactions on Computers
Re-use-centric architecture for a fully accelerated testbench environment
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 40th annual Design Automation Conference
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
Sequential circuit fault simulation using logic emulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault emulation: A new methodology for fault grading
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CMOS circuit verification with symbolic switch-level timing simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Boolean Analysis of MOS Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a method for emulating switch-level models of CMOS circuits using FPGAs. In this method, logic gates are used to model switch-level circuits without any abstraction. In contrast to the abstraction methods for which transistors are grouped together to form gates, in this method, gates are grouped together to form the switch models of transistors. The method presented in this paper, unlike the abstraction methods, can emulate many important features of switch-level models, such as bi-directional signal propagation and variations in driving strength. In order to attain a better utilization of FPGA resources a mixed-mode emulation approach has been used. In this approach parts of the circuit are emulated at the switch-level while the remaining parts of the circuit are emulated at the gate-level. The experimental results show that the presented emulation-based approach could be significantly faster than existing simulation-based approaches. The analytical performance estimation shows that the speed-up grows with the circuit size and is workload dependent.