Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Combinational static CMOS networks
Integration, the VLSI Journal
DESB, a functional abstractor for CMOS VLSI circuits
EURO-DAC '92 Proceedings of the conference on European design automation
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Automatic clock abstraction from sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Analysis of cyclic combinational circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
ITC '98 Proceedings of the 1998 IEEE International Test Conference
LICS '97 Proceedings of the 12th Annual IEEE Symposium on Logic in Computer Science
Comparing layouts with HDL models: a formal verification technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 40th annual Design Automation Conference
An automated method for test model generation from switch level circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Emulating switch-level models of CMOS circuits
Microelectronic Engineering
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A chip that is required to meet strict operating criteria in terms of speed, power, or area is commonly custom designed at the switch level. Traditional techniques for verifying these designs, based on simulation, are expensive in terms of resources and cannot completely guarantee correct operation. Formal verification methods, on the other hand, provide for a complete proof of correctness, and require less effort to setup. This paper presents Motorola's Switch Level Verification (SLV) tool, which employs detailed switch level analysis to model the behavior of MOS transistors and obtain an equivalent RTL model. This tool has been used for equivalence checking at the switch level for several years within Motorola for the PowerPC, M*Core and DSP custom blocks. We focus on the novel techniques employed in SLV, particularly in the areas of pre-charged and sequential logic analysis, and provide details on the automated and integrated equivalence checking flow in which the tool is used.