Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
COSMOS: a compiled simulator for MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
On the verification of sequential machines at differing levels of abstraction
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Mapping switch-level simulation onto gate-level hardware accelerators
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Formal hardware verification methods: a survey
Formal Methods in System Design - Special issue on computer-aided verification: general methods
Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Probabilistic construction and manipulation of free Boolean diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Analysis of cyclic combinational circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Proving circuit correctness using formal comparison between expected and extracted behaviour
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Switch-level simulation of VLSI using a special-purpose data-driven computer
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Symbolic Model Checking
Introduction to VLSI Systems
Comparing Layouts with HDL Models: A Formal Verification Technique
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Simulating pass transistor circuits using logic simulation machines
DAC '83 Proceedings of the 20th Design Automation Conference
The Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
EURO-DAC '90 Proceedings of the conference on European design automation
Functional abstraction of logic gates for switch-level simulation
EURO-DAC '91 Proceedings of the conference on European design automation
The Necessity of Closed Circuit Loops in Minimal Combinational Circuits
IEEE Transactions on Computers
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
High-level synthesis in an industrial environment
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Logic verification methodology for PowerPC microprocessors
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Formal verification of PowerPC arrays using symbolic trajectory evaluation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal methods: state of the art and future directions
ACM Computing Surveys (CSUR) - Special ACM 50th-anniversary issue: strategic directions in computing research
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
A pseudo-hierarchical methodology for high performance microprocessor design
Proceedings of the 1997 international symposium on Physical design
Standard-cell-based design methodology for high-performance support chips
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Advanced microprocessor test strategy and methodology
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Design methodologies for noise in digital integrated circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Auxiliary variables for BDD-based representation and manipulation of Boolean functions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Formal specification and verification of a dataflow processor array
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
Testing for Function and Performance: Towards anIntegrated Processor Validation Methodology
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Formal Methods in System Design
A flat, timing-driven design system for a high-performance CMOS processor chipset
Proceedings of the conference on Design, automation and test in Europe
Automated equivalence checking of switch level circuits
Proceedings of the 39th annual Design Automation Conference
Combinational and sequential equivalence checking
Logic Synthesis and Verification
Why is Combinational ATPG Efficiently Solvable for Practical VLSI Circuits?
Journal of Electronic Testing: Theory and Applications
Testing the 500-MHz IBM S/390 Microprocessor
IEEE Design & Test
IEEE Micro
Verisym: Verifying Circuits by Symbolic Simulation
Formal Methods in System Design
Formal Verification Methods for Industrial Hardware Design
SOFSEM '01 Proceedings of the 28th Conference on Current Trends in Theory and Practice of Informatics Piestany: Theory and Practice of Informatics
Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Integrating formal verification into computer organization and architecture courses
Journal of Computing Sciences in Colleges
Designing mega-ASICs in nanogate technologies
Proceedings of the 40th annual Design Automation Conference
Static noise analysis with noise windows
Proceedings of the 40th annual Design Automation Conference
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Testing The 400-MHz IBM Generation-4 CMOS Chip
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A satisfiability procedure for quantified boolean formulae
Discrete Applied Mathematics - The renesse issue on satisfiability
Functional verification of a frequency-programmable switch chip with asynchronous clock sections
IBM Journal of Research and Development
Automatic Formal Verification of Fused-Multiply-Add FPUs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Functional formal verification on designs of pSeries microprocessors and communication subsystems
IBM Journal of Research and Development - POWER5 and packaging
Improvements to combinational equivalence checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
The circuit and physical design of the POWER4 microprocessor
IBM Journal of Research and Development
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems
IBM Journal of Research and Development
Blue Gene/L compute chip: synthesis, timing, and physical design
IBM Journal of Research and Development
A BDD-based verification method for large synthesized circuits
Integration, the VLSI Journal
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