The design of a microprocessor
The design of a microprocessor
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Algorithms for large-scale flat placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
Algorithms for detailed placement of standard cells
Proceedings of the conference on Design, automation and test in Europe
Timing analysis and optimization of a high-performance CMOS processor chipset
Proceedings of the conference on Design, automation and test in Europe
A sequential detailed router for huge grid graphs
Proceedings of the conference on Design, automation and test in Europe
In the Driver's Seat of BooleDozer
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Algorithms for large-scale flat placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
Analysis, reduction and avoidance of crosstalk on VLSI chips
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Cycle time and slack optimization for VLSI-chips
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Static timing analysis taking crosstallk into account
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Algorithms for detailed placement of standard cells
Proceedings of the conference on Design, automation and test in Europe
Timing analysis and optimization of a high-performance CMOS processor chipset
Proceedings of the conference on Design, automation and test in Europe
A sequential detailed router for huge grid graphs
Proceedings of the conference on Design, automation and test in Europe
Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip
Discrete Applied Mathematics
Geometric quadrisection in linear time, with application to VLSI placement
Discrete Optimization
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We describe the methodology used for the design of the CMOS processor chipset used in the IBM S/390 Parallel Enterprise Server - Generation 3. The majority of the logic is implemented by standard cell elements placed and routed flat, using timing-driven techniques. The result is a globally optimized solution without artificial floorplan boundaries. We will show that the density in terms of transistors per mm2 is comparable to the most advanced custom designs and that the impact of interconnect delay on the cycle time is very small. Compared to custom design, this approach offers excellent turn-around-time and considerably reduces overall effort.