IEEE Transactions on Computers
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimal clock skew scheduling tolerant to process variations
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S/390 parallel enterprise server generation 3: a balanced system and cache structure
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Graph algorithms for clock schedule optimization
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A flat, timing-driven design system for a high-performance CMOS processor chipset
Proceedings of the conference on Design, automation and test in Europe
A practical clock tree synthesis for semi-synchronous circuits
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
The IBM ASIC/SoC methodology--A recipe for first-time success
IBM Journal of Research and Development
Clock Scheduling and Clocktree Construction for High Performance ASICS
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multi-Domain Clock Skew Scheduling
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Experimental analysis of the fastest optimum cycle ratio and mean algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Yield-Driven, False-Path-Aware Clock Skew Scheduling
IEEE Design & Test
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Skew scheduling and clock routing for improved tolerance to process variations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Clock Skew Scheduling Under Process Variations
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Integrated placement and skew optimization for rotary clocking
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Efficient incremental clock latency scheduling for large circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Register binding for clock period minimization
Proceedings of the 43rd annual Design Automation Conference
ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling
Proceedings of the 43rd annual Design Automation Conference
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Physical aware clock skew rescheduling
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Clock skew scheduling with race conditions considered
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clock period minimization with minimum delay insertion
Proceedings of the 44th annual Design Automation Conference
Integrated placement and skew optimization for rotary clocking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast incremental clock skew scheduling algorithm for slack optimization
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Multi-level clustering for clock skew optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
A practical method for multi-domain clock skew optimization
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Online clock skew tuning for timing speculation
Proceedings of the International Conference on Computer-Aided Design
A statistical approach to the timing-yield optimization of pipeline circuits
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Clock skew scheduling for timing speculation
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
SmipRef: An efficient method for multi-domain clock skew scheduling
Integration, the VLSI Journal
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We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes all previously considered models. Then we show how to optimize the cycle time and optimally balance slacks on data paths and on clocktree paths.The problem of finding a clock schedule with the optimum cycle time was solved before, either by linear programming or by binary search, using a test for negative circuits in a digraph as a subroutine. We show for the first time that a direct combinatorial algorithm solves this problem optimally. Incidentally, this yields a new efficient method for timing analysis with transparent latches.Moreover, we extend this algorithm to the slack balancing problem: To make the chip less sensitive to routing detours, process variations and manufacturing skew it is desirable to have as few critical paths as possible. We show how to find the clock schedule with minimum number of critical paths (optimum slack distribution) in a well-defined sense. Rather than fixed clock arrival times we show how to obtain as large as possible intervals for the clock arrival times. This can be considered as slack on clocktree paths. Indeed, we can find the global optimum of simultaneous optimization of slacks on all data paths and clocktree paths.All the above is done by very efficient network optimization algorithms, based on parametric shortest paths. Our computational results with recent IBM processor chips show that the number of critical paths decreases dramatically, in addition to a considerable improvement of the cycle time. The running times are reasonable even for the largest designs.