Yield-Driven, False-Path-Aware Clock Skew Scheduling

Authors:
Jeng-Liang Tsai;Dong Hyun Baik;Charlie Chung-Ping Chen;Kewal K. Saluja
Affiliations:
University of Wisconsin-Madison;University of Wisconsin-Madison;University of Wisconsin-Madison;University of Wisconsin-Madison
Venue:
IEEE Design & Test
Year:
2005

Citing 8
Cited 4

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Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays

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Online clock skew tuning for timing speculation

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DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe

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Abstract

This article proposes clock skew scheduling as a tool to address causes of performance-related circuit yield loss. It is an interesting example of how managing circuit-level parameters can have a direct impact on yield metrics and, therefore, a clear example of the direction of DFM research.