Clock skew scheduling for timing speculation

Authors:
Rong Ye;Feng Yuan;Hai Zhou;Qiang Xu
Affiliations:
The Chinese University of Hong Kong, Shatin, N.T., Hong Kong and Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences;The Chinese University of Hong Kong, Shatin, N.T., Hong Kong;Northwestern University;The Chinese University of Hong Kong, Shatin, N.T., Hong Kong and Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences
Venue:
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2012

Citing 15
Cited 0

Clock Skew Optimization

IEEE Transactions on Computers
Cycle time and slack optimization for VLSI-chips

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Clock skew scheduling for improved reliability via quadratic programming

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation

Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Yield-Driven, False-Path-Aware Clock Skew Scheduling

IEEE Design & Test
Deployment of Better Than Worst-Case Design: Solutions and Needs

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Clock Skew Scheduling Under Process Variations

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Clock period minimization with minimum delay insertion

Proceedings of the 44th annual Design Automation Conference
Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays

Proceedings of the 45th annual Design Automation Conference
Timing Optimization Through Clock Skew Scheduling

Timing Optimization Through Clock Skew Scheduling
EVAL: Utilizing processors with variation-induced timing errors

Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Circuit techniques for dynamic variation tolerance

Proceedings of the 46th Annual Design Automation Conference
Re-synthesis for cost-efficient circuit-level timing speculation

Proceedings of the 48th Design Automation Conference
Online clock skew tuning for timing speculation

Proceedings of the International Conference on Computer-Aided Design
On timing-independent false path identification

Proceedings of the International Conference on Computer-Aided Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

By assigning intentional clock arrival times to the sequential elements in a circuit, clock skew scheduling (CSS) techniques can be utilized to improve IC performance. Existing CSS solutions work in a conservative manner that guarantees "always correct" computation, and hence their effectiveness is greatly challenged by the ever-increasing process variation effects. By allowing infrequent timing errors and recovering from them with minor performance impact, timing speculation techniques such as Razor have gained wide interests from both academia and industry. In this work, we formulate the clock skew scheduling problem for circuits equipped with timing speculation capability and propose a novel CSS algorithm based on gradient-descent method. Experimental results on various benchmark circuits demonstrate the effectiveness of our proposed methodology.