Delay Testing of Digital Circuits by Output Waveform Analysis
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Optimizing pipelines for power and performance
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
The optimum pipeline depth considering both power and performance
ACM Transactions on Architecture and Code Optimization (TACO)
An on-chip NBTI sensor for measuring PMOS threshold voltage degradation
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Circuit techniques for dynamic variation tolerance
Proceedings of the 46th Annual Design Automation Conference
Circuit techniques for dynamic variation tolerance
Proceedings of the 46th Annual Design Automation Conference
Overscaling-friendly timing speculation architectures
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Design techniques for cross-layer resilience
Proceedings of the Conference on Design, Automation and Test in Europe
TIMBER: time borrowing and error relaying for online timing error resilience
Proceedings of the Conference on Design, Automation and Test in Europe
A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Re-synthesis for cost-efficient circuit-level timing speculation
Proceedings of the 48th Design Automation Conference
Architecting processors to allow voltage/reliability tradeoffs
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Analysis of circuit dynamic behavior with timed ternary decision diagram
Proceedings of the International Conference on Computer-Aided Design
Row-based FBB: A design-time optimization for post-silicon tunable circuits
Microelectronics Journal
Recovery-based design for variation-tolerant SoCs
Proceedings of the 49th Annual Design Automation Conference
CCP: common case promotion for improved timing error resilience with energy efficiency
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures
Proceedings of the 39th Annual International Symposium on Computer Architecture
Journal of Electronic Testing: Theory and Applications
On logic synthesis for timing speculation
Proceedings of the International Conference on Computer-Aided Design
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Exploiting Timing Error Resilience in Processor Architecture
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
Proceedings of the Conference on Design, Automation and Test in Europe
Hierarchically focused guardbanding: an adaptive approach to mitigate PVT variations and aging
Proceedings of the Conference on Design, Automation and Test in Europe
Efficiently tolerating timing violations in pipelined microprocessors
Proceedings of the 50th Annual Design Automation Conference
Relax-and-retime: a methodology for energy-efficient recovery based design
Proceedings of the 50th Annual Design Automation Conference
InTimeFix: a low-cost and scalable technique for in-situ timing error masking in logic circuits
Proceedings of the 50th Annual Design Automation Conference
Compact current source models for timing analysis under temperature and body bias variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scaling energy per operation via an asynchronous pipeline
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A resilient architecture for low latency communication in shared-L1 processor clusters
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Clock skew scheduling for timing speculation
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Analysis of instruction-level vulnerability to dynamic voltage and temperature variations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 21st International conference on Real-Time Networks and Systems
Virtually-aged sampling DMR: unifying circuit failure prediction and circuit failure detection
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Implicit-storing and redundant-encoding-of-attribute information in error-correction-codes
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Modeling the impact of permanent faults in caches
ACM Transactions on Architecture and Code Optimization (TACO)
ForTER: a forward error correction scheme for timing error resilience
Proceedings of the International Conference on Computer-Aided Design
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Three circuit techniques for dynamic variation tolerance are presented: (i) Sensors with adaptive voltage and frequency circuits, (ii) Tunable replica circuits for timing-error prediction with error recovery, and (iii) Embedded error-detection sequential circuits with error recovery. These circuits mitigate the clock frequency guardbands for dynamic variations, thus improving microprocessor performance and energy-efficiency. These circuits are described with a focus on the different trade-offs in guardband reduction and design overhead. Opportunities for CAD to further enhance microprocessor performance and energy efficiency are offered.