Transition density, a stochastic measure of activity in digital circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Improving the accuracy of circuit activity measurement
DAC '94 Proceedings of the 31st annual Design Automation Conference
Switching activity analysis using Boolean approximation method
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Efficient estimation of dynamic power consumption under a real delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Switching activity estimation using limited depth reconvergent path analysis
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Dependency preserving probabilistic modeling of switching activity using bayesian networks
Proceedings of the 38th annual Design Automation Conference
Satisfiability models and algorithms for circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Ternary Decision Diagrams: Survey
ISMVL '97 Proceedings of the 27th International Symposium on Multiple-Valued Logic
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Efficient Boolean characteristic function for fast timed ATPG
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Circuit techniques for dynamic variation tolerance
Proceedings of the 46th Annual Design Automation Conference
DynaTune: circuit-level optimization for timing speculation considering dynamic path behavior
Proceedings of the 2009 International Conference on Computer-Aided Design
Slack redistribution for graceful degradation under voltage overscaling
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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Modern logic optimization tools tend to optimize circuits in a balanced way so that all primary outputs (POs) have similar delay close to the cycle time. However, certain POs will be exercised more frequently than the rest. Among these critical primary outputs, some may be stabilized very quickly by input vectors, even if their topological delays from primary inputs are very long. Knowing the dynamic behavior of a circuit can help optimize the most commonly activated paths and help engineers understand how resilient a PO is against dynamic environmental variations such as voltage fluctuations. In this paper, we describe a tool to analyze the dynamic behavior of a circuit utilizing probabilistic information. The techniques exploit the use of timed ternary decision diagrams (tTDD) to encode stabilization conditions for POs. To compute probabilities based on a tTDD, we propose false assignment pruning and random variable compaction to preserve probability calculation accuracy. To deal with the scalability issue, this paper proposes a new circuit partitioning heuristic to reduce the inaccuracy introduced by partitioning. Compared to the timed simulation results, our tool has a mean absolute error of 2.5% and a root mean square error of 5.3% on average for ISCAS-85 benchmarks. Compared to a state-of-the-art dynamic behavior analysis tool, our tool is on average 40x faster and can handle circuits that the previous tool cannot.