Transition density, a stochastic measure of activity in digital circuits

Estimation of average switching activity in combinational and sequential circuits

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference

Technology decomposition and mapping targeting low power dissipation

DAC '93 Proceedings of the 30th international Design Automation Conference

Surveys in combinatorics, 1993

Surveys in combinatorics, 1993

Re-encoding sequential circuits to reduce power dissipation

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Precomputation-based sequential logic optimization for low power

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Switching activity analysis considering spatiotemporal correlations

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Estimation of circuit activity considering signal correlations and simultaneous switching

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

A symbolic method to reduce power consumption of circuits containing false paths

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Multi-level network optimization for low power

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Logic synthesis for reliability—an early start to controlling electromigration and hot carrier effects

EURO-DAC '94 Proceedings of the conference on European design automation

A new power estimation technique with application to decomposition of Boolean functions for low power

EURO-DAC '94 Proceedings of the conference on European design automation

Feedback, correlation, and delay concerns in the power estimation of VLSI circuits

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs

ISLPED '95 Proceedings of the 1995 international symposium on Low power design

Simultaneous scheduling and binding for power minimization during microarchitecture synthesis

ISLPED '95 Proceedings of the 1995 international symposium on Low power design

High-level synthesis techniques for reducing the activity of functional units

ISLPED '95 Proceedings of the 1995 international symposium on Low power design

The design and implementation of PowerMill

ISLPED '95 Proceedings of the 1995 international symposium on Low power design

Guarded evaluation: pushing power management to logic synthesis/design

ISLPED '95 Proceedings of the 1995 international symposium on Low power design

An estimation technique to guide low power resynthesis algorithms

ISLPED '95 Proceedings of the 1995 international symposium on Low power design

Switching activity analysis using Boolean approximation method

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Boolean techniques for low power driven re-synthesis

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Power vs. delay in gate sizing: conflicting objectives?

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Transistor reordering for power minimization under delay constraint

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Electromigration reliability enhancement via bus activity distribution

DAC '96 Proceedings of the 33rd annual Design Automation Conference

A new hybrid methodology for power estimation

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Stochastic sequential machine synthesis targeting constrained sequence generation

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Switching activity analysis for sequential circuits using Boolean approximation method

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design

Effects of correlations on accuracy of power analysis—an experimental study

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design

Integrated resynthesis for low power

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design

Efficient estimation of dynamic power consumption under a real delay model

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Retiming sequential circuits for low power

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

A method of redundant clocking detection and power reduction at RT level design

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design

Switching activity estimation using limited depth reconvergent path analysis

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design

Low power multiplexer decomposition

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design

Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks

DAC '97 Proceedings of the 34th annual Design Automation Conference

Power sensitivity—a new method to estimate power dissipation considering uncertain specifications of primary inputs

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Minimizing interconnect energy through integrated low-power placement and combinational logic synthesis

Proceedings of the 1997 international symposium on Physical design

Low power logic synthesis under a general delay model

ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design

A power optimization method considering glitch reduction by gate sizing

ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks

ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design

Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis

Journal of VLSI Signal Processing Systems - Special issue on systematic trade-off analysis in signal processing systems design

Two-level logic minimization for low power

ACM Transactions on Design Automation of Electronic Systems (TODAES)

McPOWER: a Monte Carlo approach to power estimation

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

HYPER-LP: a system for power minimization using architectural transformations

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

On average power dissipation and random pattern testability of CMOS combinational logic networks

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

A practical gate resizing technique considering glitch reduction for low power design

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Power-delay optimizations in gate sizing

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Analytical macromodeling for high-level power estimation

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Stochastic sequential machine synthesis with application to constrained sequence generation

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A static power estimation methodolodgy for IP-based design

Proceedings of the conference on Design, automation and test in Europe

G-vector: A New Model for Glitch Analysis in Logic Circuits

Journal of VLSI Signal Processing Systems

Low power address encoding using self-organizing lists

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design

Sentry tag: an efficient filter scheme for low power cache

CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture

Retiming-based logic synthesis for low-power

Proceedings of the 2002 international symposium on Low power electronics and design

Bus optimization for low-power data path synthesis based on network flow method

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

An integrated data path optimization for low power based on network flow method

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

Fast Power Estimation of Large Circuits

IEEE Design & Test

Low power design and its testability

ATS '95 Proceedings of the 4th Asian Test Symposium

Optimization of combinational and sequential logic circuits for low power using precomputation

ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)

Optimizing CMOS Circuits for Low Power Using Transistor Reordering

EDTC '96 Proceedings of the 1996 European conference on Design and Test

Switch level hot-carrier reliability enhancement of VLSI circuits

DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

A symbolic simulation approach in resolving signals' correlation

SS '96 Proceedings of the 29th Annual Simulation Symposium (SS '96)

Circuit optimization for minimisation of power consumption under delay constraint

VLSID '95 Proceedings of the 8th International Conference on VLSI Design

Maximum power estimation for CMOS circuits using deterministic and statistic approaches

VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication

20.3 A Test Pattern Generation Methodology for Low-Power Consumption

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

DS-LFSR: A New BIST TPG for Low Heat Dissipation

ITC '97 Proceedings of the 1997 IEEE International Test Conference

High-level synthesis for low power based on network flow method

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)

High-level macro-modeling and estimation techniques for switching activity and power consumption

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Adaptive low-power address encoding techniques using self-organizing lists

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power

Leakage current estimation of CMOS circuit with stack effect

Journal of Computer Science and Technology - Special issue on computer graphics and computer-aided design

LAP: a logic activity packing methodology for leakage power-tolerant FPGAs

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design

HyPE: hybrid power estimation for IP-based programmable systems

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

FLAW: FPGA lifetime awareness

Proceedings of the 43rd annual Design Automation Conference

Low Power VLSI Design Techniques - The Current State

Integrated Computer-Aided Engineering

Logic synthesis for reducing leakage power consumption under workload uncertainty

ICC'08 Proceedings of the 12th WSEAS international conference on Circuits

DynaTune: circuit-level optimization for timing speculation considering dynamic path behavior

Proceedings of the 2009 International Conference on Computer-Aided Design

Full-chip leakage analysis for 65nm CMOS technology and beyond

Integration, the VLSI Journal

Maximum power estimation for CMOS circuits using deterministic and statistical approaches

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Efficient statistical approach to estimate power considering uncertain properties of primary inputs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Analysis of circuit dynamic behavior with timed ternary decision diagram

Proceedings of the International Conference on Computer-Aided Design

A Probabilistic Approach to Diagnose SETs in Sequential Circuits

Journal of Electronic Testing: Theory and Applications