Two-level logic minimization for low power

Authors:
Jyh-Mou Tseng;Jing-Yang Jou
Affiliations:
ITRI, Hsinchu, Taiwan;National Chiao Tung Univ., Hsinchu, Taiwan
Venue:
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Year:
1999

Citing 9
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Abstract

In this paper we present a complete Boolean method for reducing the power consumption in two-level combinational circuits. The two-level logic optimizer performs the logic minimization for low power targeting static PLA, general logic gates, and dynamic PLA implementations. We modify the espresso algorithm by adding our heuristics, which bias logic minimization toward lowering power dissipation. In our heuristics, signal probabilities and transition densities are two important parameters. The experimental results are promising.