Estimation of average switching activity in combinational and sequential circuits

Technology decomposition and mapping targeting low power dissipation

DAC '93 Proceedings of the 30th international Design Automation Conference

Surveys in combinatorics, 1993

Surveys in combinatorics, 1993

Re-encoding sequential circuits to reduce power dissipation

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Precomputation-based sequential logic optimization for low power

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Switching activity analysis considering spatiotemporal correlations

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Estimation of circuit activity considering signal correlations and simultaneous switching

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

A cell-based power estimation in CMOS combinational circuits

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

A symbolic method to reduce power consumption of circuits containing false paths

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Optimization of hierarchical designs using partitioning and resynthesis

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

A methodology for efficient estimation of switching activity in sequential logic circuits

DAC '94 Proceedings of the 31st annual Design Automation Conference

Exact and approximate methods for calculating signal and transition probabilities in FSMs

DAC '94 Proceedings of the 31st annual Design Automation Conference

Technology mapping using fuzzy logic

DAC '94 Proceedings of the 31st annual Design Automation Conference

Improving the accuracy of circuit activity measurement

DAC '94 Proceedings of the 31st annual Design Automation Conference

A new power estimation technique with application to decomposition of Boolean functions for low power

EURO-DAC '94 Proceedings of the conference on European design automation

A survey of optimization techniques targeting low power VLSI circuits

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Accurate estimation of combinational circuit activity

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Extreme delay sensitivity and the worst-case switching activity in VLSI circuits

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Efficient power estimation for highly correlated input streams

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs

ISLPED '95 Proceedings of the 1995 international symposium on Low power design

Simultaneous scheduling and binding for power minimization during microarchitecture synthesis

ISLPED '95 Proceedings of the 1995 international symposium on Low power design

High-level synthesis techniques for reducing the activity of functional units

ISLPED '95 Proceedings of the 1995 international symposium on Low power design

CMOS dynamic power estimation based on collapsible current source transistor modeling

ISLPED '95 Proceedings of the 1995 international symposium on Low power design

Guarded evaluation: pushing power management to logic synthesis/design

ISLPED '95 Proceedings of the 1995 international symposium on Low power design

An estimation technique to guide low power resynthesis algorithms

ISLPED '95 Proceedings of the 1995 international symposium on Low power design

Switching activity analysis using Boolean approximation method

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Estimation and bounding of energy consumption in burst-mode control circuits

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Statistical estimation of sequential circuit activity

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Boolean techniques for low power driven re-synthesis

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Power estimation techniques for integrated circuits

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Delay optimal partitioning targeting low power VLSI circuits

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Power minimization in IC design: principles and applications

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Transistor reordering for power minimization under delay constraint

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry

IEEE Transactions on Computers

POSE: power optimization and synthesis environment

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Compact vector generation for accurate power simulation

DAC '96 Proceedings of the 33rd annual Design Automation Conference

A new hybrid methodology for power estimation

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Stochastic sequential machine synthesis targeting constrained sequence generation

DAC '96 Proceedings of the 33rd annual Design Automation Conference

An exact algorithm for low power library-specific gate re-sizing

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Desensitization for power reduction in sequential circuits

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Hot-carrier reliability enhancement via input reordering and transistor sizing

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Inaccuracies in power estimation during logic synthesis

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Stratified random sampling for power estimation

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Expected current distributions for CMOS circuits

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

State assignment for FSM low power design

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

A novel methodology for transistor-level power estimation

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design

Effects of correlations on accuracy of power analysis—an experimental study

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design

Basic experimentation on accuracy of power estimation for CMOS VLSI circuits

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design

Symbolic computation of logic implications for technology-dependent low-power synthesis

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design

Logic synthesis using power-sensitive don't care sets

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design

Efficient estimation of dynamic power consumption under a real delay model

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Retiming sequential circuits for low power

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Engineering change for power optimization using global sensitivity and synthesis flexibility

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design

K2: an estimator for peak sustainable power of VLSI circuits

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design

Low power multiplexer decomposition

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design

Node normalization and decomposition in low power technology mapping

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design

A gate resizing technique for high reduction in power consumption

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design

High-level power modeling, estimation, and optimization

DAC '97 Proceedings of the 34th annual Design Automation Conference

Analytical estimation of transition activity from word-level signal statistics

DAC '97 Proceedings of the 34th annual Design Automation Conference

Power sensitivity—a new method to estimate power dissipation considering uncertain specifications of primary inputs

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Effects of delay models on peak power estimation of VLSI sequential circuits

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Minimizing interconnect energy through integrated low-power placement and combinational logic synthesis

Proceedings of the 1997 international symposium on Physical design

Power invariant vector compaction based on bit clustering and temporal partitioning

ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks

ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design

Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis

Journal of VLSI Signal Processing Systems - Special issue on systematic trade-off analysis in signal processing systems design

PowerDrive: a fast, canonical POWER estimator for DRIVing synthEsis

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Two-level logic minimization for low power

ACM Transactions on Design Automation of Electronic Systems (TODAES)

HYPER-LP: a system for power minimization using architectural transformations

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

On average power dissipation and random pattern testability of CMOS combinational logic networks

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Peak power estimation using genetic spot optimization for large VLSI circuits

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Dynamic power estimation using the probabilistic contribution measure (PCM)

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design

Power-delay optimizations in gate sizing

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Power optimization of technology-dependent circuits based on symbolic computation of logic implications

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Stochastic sequential machine synthesis with application to constrained sequence generation

ACM Transactions on Design Automation of Electronic Systems (TODAES)

G-vector: A New Model for Glitch Analysis in Logic Circuits

Journal of VLSI Signal Processing Systems

Dependency preserving probabilistic modeling of switching activity using bayesian networks

Proceedings of the 38th annual Design Automation Conference

Sentry tag: an efficient filter scheme for low power cache

CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture

Fast Power Estimation of Large Circuits

IEEE Design & Test

Prediction of Power Requirements for High-Speed Circuits

Real-World Applications of Evolutionary Computing, EvoWorkshops 2000: EvoIASP, EvoSCONDI, EvoTel, EvoSTIM, EvoROB, and EvoFlight

Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level

PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation

Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT

Journal of VLSI Signal Processing Systems

Low power design and its testability

ATS '95 Proceedings of the 4th Asian Test Symposium

Optimization of combinational and sequential logic circuits for low power using precomputation

ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)

Decomposition of logic functions for minimum transition activity

EDTC '95 Proceedings of the 1995 European conference on Design and Test

Improving the Accuracy of Support-Set Finding Method for Power Estimation of Combinational Circuits

EDTC '97 Proceedings of the 1997 European conference on Design and Test

Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model

EDTC '97 Proceedings of the 1997 European conference on Design and Test

Switch level hot-carrier reliability enhancement of VLSI circuits

DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

A symbolic simulation approach in resolving signals' correlation

SS '96 Proceedings of the 29th Annual Simulation Symposium (SS '96)

Estimation of Power from Module-level Netlists

VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication

A Real Delay Switching Activity Simulator based on Petri net Modeling

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

20.3 A Test Pattern Generation Methodology for Low-Power Consumption

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

A Test Vector Inhibiting Technique for Low Energy BIST Design

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

Probabilistic Bottom-Up RTL Power Estimation

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

Switching activity estimation of VLSI circuits using Bayesian networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Petri net modeling of gate and interconnect delays for power estimation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power

Exploiting FPGA concurrency to enhance JVM performance

ACSC '04 Proceedings of the 27th Australasian conference on Computer science - Volume 26

Any-time probabilistic switching model using bayesian networks

Proceedings of the 2004 international symposium on Low power electronics and design

Implicit Resolution of the Chapman-Kolmogorov Equations for Sequential Circuits: An Application in Power Estimation

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages

Proceedings of the 42nd annual Design Automation Conference

Sign bit reduction encoding for low power applications

Proceedings of the 42nd annual Design Automation Conference

Synthesis of high performance low power PTL circuits

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Improved Boolean function hashing based on multiple-vertex dominators

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Low-power tradeoffs for mobile computing applications: embedded processors versus custom computing kernels

ACM-SE 45 Proceedings of the 45th annual southeast regional conference

A timing dependent power estimation framework considering coupling

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Low Power VLSI Design Techniques - The Current State

Integrated Computer-Aided Engineering

Power Estimation Under Uncertain Delays

Integrated Computer-Aided Engineering

A Technique for Estimating Signal Activity in Logic Circuits

Integrated Computer-Aided Engineering

Techniques for maintaining connectivity in wireless ad-hoc networks under energy constraints

ACM Transactions on Embedded Computing Systems (TECS)

Effecting power consumption reduction in digital CMOS circuits by a hybrid logic synthesis technique

ESPOCO'05 Proceedings of the 4th WSEAS International Conference on Electronic, Signal Processing and Control

Signal probability based statistical timing analysis

Proceedings of the conference on Design, automation and test in Europe

Bounds on FSM Switching Activity

Journal of Signal Processing Systems

Power estimation technique for DSP architectures

Digital Signal Processing

Generating Worst-Case Stimuli for Accurate Power Grid Analysis

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Satisfiability models for maximum transition power

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Evolutionary algorithms for VLSI multi-objective netlist partitioning

Engineering Applications of Artificial Intelligence

Decomposition-based vectorless toggle rate computation for FPGA circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A timing-dependent power estimation framework considering coupling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Cascaded Bayesian inferencing for switching activity estimation with correlated inputs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Finding the energy efficient curve: gate sizing for minimum power under delay constraints

VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions

Efficient statistical approach to estimate power considering uncertain properties of primary inputs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Analysis of the conditions for the worst case switching activity in integrated circuits

Analog Integrated Circuits and Signal Processing

Toward PDN resource estimation: a law of general power density

Proceedings of the System Level Interconnect Prediction Workshop

Logic-Level fast current simulation for digital CMOS circuits

PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

Statistical full-chip total power estimation considering spatially correlated process variations

Integration, the VLSI Journal

A Probabilistic Approach to Diagnose SETs in Sequential Circuits

Journal of Electronic Testing: Theory and Applications

An Analytical Model for Evaluating Static Power of Homogeneous FPGA Architectures

ACM Transactions on Reconfigurable Technology and Systems (TRETS)