G-vector: A New Model for Glitch Analysis in Logic Circuits

Authors:
Ki-Seok Chung;Taewhan Kim;C. L. Liu
Affiliations:
Design Technology, Intel Corporation, Santa Clara, CA 95052, USA;Dept. of Electrical Engineering & Computer Science and Advanced Information Technology Research Center (AITrc), Korea Advanced Institute of Science & Technology, Taejon, Korea;Dept. of Computer Science, Tsing Hua University, Hsinchu, Taiwan, R.O.C.
Venue:
Journal of VLSI Signal Processing Systems
Year:
2001

Citing 14
Cited 1

Uncertainty, Energy, and Multiple-Valued Logics

IEEE Transactions on Computers
Transition density, a stochastic measure of activity in digital circuits

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Estimation of average switching activity in combinational and sequential circuits

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Accurate estimation of combinational circuit activity

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Analysis of glitch power dissipation in CMOS ICs

ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Power minimization in IC design: principles and applications

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Pattern-independent current estimation for reliability analysis of CMOS circuits

DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Low Power Digital CMOS Design

Low Power Digital CMOS Design
Decomposition of logic functions for minimum transition activity

EDTC '95 Proceedings of the 1995 European conference on Design and Test
Hazard detection by a quinary simulation of logic devices with bounded propagation delays

DAC '72 Proceedings of the 9th Design Automation Workshop
An approach for multilevel logic optimization targeting low power

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Probabilistic modeling of dependencies during switching activity analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Stratified random sampling for power estimation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate-level power estimation using tagged probabilistic simulation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Crosstalk-glitch gating: a solution for designing glitch-tolerant asynchronous handshake interface mechanisms for GALS systems

IEEE Transactions on Circuits and Systems Part I: Regular Papers

Quantified Score

Hi-index	0.01

Visualization

Abstract

One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many of such switching activities are due to spurious pulses, called glitches. In this paper, we propose a new model for describing signals that contain glitches, called G-vector. Unlike the previous works in which their primary concern is modeling the propagation of glitches to count the number of glitches in the circuits, our G-vector provides a general, but effective model for generation, propagation and elimination of glitches, enabling us to not only count the number of glitches but also locate the glitches so that such information can be utilized by system tools for the reduction of the number of glitches in the circuits. We provide a set of experimental results to demonstrate the effectiveness of our model.