G-vector: A New Model for Glitch Analysis in Logic Circuits
Journal of VLSI Signal Processing Systems
Least-square estimation of average power in digital CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application-driven processor design exploration for power-performance trade-off analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Circuit power estimation using pattern recognition techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Power estimation of CMOS circuits by neural network macromodel
ISNN'06 Proceedings of the Third international conference on Advances in Neural Networks - Volume Part III
Statistical full-chip total power estimation considering spatially correlated process variations
Integration, the VLSI Journal
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In this paper, we present new statistical sampling techniques for performing power estimation at the circuit level. These techniques first transform the power estimation problem to a survey sampling problem, and then apply stratified random sampling to improve the efficiency of sampling. The stratification is based on a low-cost predictor, such as the zero-delay power estimate. We also propose a two-stage stratified sampling technique to handle very long initial sequences. Experimental results show that the efficiency of stratified random sampling and two-stage stratified sampling techniques are 3-10 times higher than that of simple random sampling and the Markov-based Monte Carlo simulation techniques