Statistical full-chip total power estimation considering spatially correlated process variations

Authors:
Zhigang Hao;Sheldon X. -D. Tan;Guoyong Shi
Affiliations:
School of Microelectronics, Shanghai Jiao Tong University, Shanghai 200240, China;Department of Electrical Engineering, University of California, Riverside, CA 92521, USA;School of Microelectronics, Shanghai Jiao Tong University, Shanghai 200240, China
Venue:
Integration, the VLSI Journal
Year:
2013

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Abstract

In this paper, we propose an efficient statistical full-chip total power estimation method considering process variations with spatial correlation. Traditionally, dynamic power and leakage power were computed separately as leakage power is more susceptible to process variations. But in the end, it is total power that designers will be concerned with. We propose a new method to compute the statistical total power via circuit level simulation under realistic input testing vectors. To consider the process variations with spatial correlation, we first apply principle factor analysis method (PFA) or its weighted version (wPFA) to transform the correlated variables into uncorrelated ones and meanwhile reduce the number of resulting random variables. Afterwards, Hermite orthogonal polynomials and sparse grid techniques are used to estimate total power distribution in a sampling way. The proposed method has no restrictions on models of statistical distributions for total powers. The method works well when strong spatial correlation exists among random variables in the chip. Experimental results show that the proposed method has 100X times speedup than the Monte Carlo method under fixed input vector and 20X times speedup than the Monte Carlo method considering both random input vectors and process variations with spatial correlation.