Power estimation technique for DSP architectures
Digital Signal Processing
Statistical full-chip total power estimation considering spatially correlated process variations
Integration, the VLSI Journal
Scalable methods for analyzing the circuit failure probability due to gate oxide breakdown
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The authors investigate a power estimation technique for VLSI that combines the accuracy of simulation-based techniques with the speed of the probabilistic techniques. The resulting method is statistical in nature; it consists of applying randomly generated input patterns to the circuit and monitoring, with a simulator, the resulting power value. This is continued until a value of power is obtained with a desired accuracy, at a specified confidence level. The authors present the algorithm and experimental results, and discuss the superiority of the approach.